1. Field of the Invention
The present invention relates to a multi-computer system in which a single or plural independent host computers share a single or plural shared IO devices and each of the host computers issues a transaction optionally.
2. Description of the Related Art
Conventionally, if it is desired that the IO (input output) bus in a host computer (hereinafter referred to as "host") is extended so as to be connected to a larger number of IO devices, or connected to an extended IO apparatus physically apart from it, a bus bridge has been generally used ("Serialization of ISA bus for transmission up to 100 m through an optical fiber": Nikkei Electronics 1994.8.22 (no. 615) p119 -p129). The bus bridge mechanism has a configuration as shown in FIG. 17. In FIG. 17, reference numeral 1 denotes a host, 2: an extended IO apparatus including an IO device such as an IO card, 3: an IO bus within the host 1, 40: an IO card connected to the IO bus 3, and 5: an IO host adaptor connected to the IO bus 3. The IO host adaptor 5 includes an IO bus interface 51, a transaction packet processing unit 53 and a transmission path interface 54 located in order from the side of the IO bus 3.
Numeral 6 denotes an IO extension cable which connects the host 1 and the extended IO apparatus 2, and 7: an IO port adaptor connected to the IO bus 8 within the extended IO apparatus. The IO port adaptor 7 also includes an IO bus interface 74, a transaction packet processing unit 73 and a host transmission path interface 71 located in order from the side of the IO bus 8. Numerals 42 and 43 denote IO cards connected to IO bus 8, respectively, and reference numeral 10 denotes a CPU (central processing unit) located within the host 1. The transmission path interface 54 of the host 1 is connected to the host transmission path interface 71 of the extended IO apparatus 2 through the IO extension cable 6.
When a transaction for the IO cards 42 and 43 on the side of the extended IO apparatus 2 generates on the IO bus 3 of the host 1, the IO host adaptor 5 selectively captures this transaction. Then, the transaction is packetted in accordance with the packet format which is previously defined according to the kind, and transmitted to the IO port adaptor 7 on the side of the extended IO apparatus 2 via the IO extension cable 6. The IO port adaptor 7 decodes the packet information so that the transaction issued on the IO bus 3 of the original host 1 is issued on the IO bus 8 within the extended IO apparatus 2.
Thus, the CPU 10 of the host 1 only issues the transaction while designating the values "100", "300" and "400" of the IO card addresses applied to the IO cards 40, 42 and 43, respectively so as to access these IO cards freely without being conscious about distinction among the IO card 40 connected to the internal IO bus 2 and the IO cards 42 and 43 connected to the IO bus 8 of the extended apparatus 2.
Meanwhile, connecting all parallel bus signals, as they are, to the extended IO apparatus 2 increases the number of signal lines of the IO extension cable 6, and cannot lengthen the signal line. For this reason, the above bus bridge mechanism serializes the packetted bus signal before supplying it onto the transmission path of the IO extension cable 6. In this way, the transaction on the IO bus 3 can be created again on the IO bus 8 of the extended IO apparatus 2. Therefore, the IO cards 42 and 43 on the IO bus 8 can be operated completely compatibly with the IO card 40 connected to the IO bus 3 of the host 1.
The bus bridge mechanism, however, can basically support only the one-to-one connection between a single host 1 and a single extended IO apparatus 2. For example, in order to connect two hosts to a single extended IO apparatus serving as a shared IO device, the above bus bridge mechanism can be used in an arrangement as shown in FIG. 18 in which the same reference numerals designate the corresponding elements in FIG. 17. In FIG. 18, reference numeral 11 denotes an inter-host communication network for communication between hosts 1A and 1B.
In such an arrangement, when two hosts 1A and 1B are to access the shared extended IO apparatus 2, competition control between the hosts 1A and 1B has to be performed. However, the IO port adaptors 7A and 7B respectively do not have the function of competition control, because they merely correspond to a signal host connection. Therefore, the competition control between the hosts 1A and 1B has to be performed by a separate route using the inter-host communication network 11 before the hosts 1A and 1B issue transactions for the IO buses 3A and 3B, respectively. Otherwise, bus arbitration between the IO port adaptors 7A and 7B have to be performed.
Further, if the plural hosts 1A and 1B share the extended IO apparatus 2, each of the hosts 1A and 1B have to map, in its own IO space, the IO devices 42 and 43 in the extended IO apparatus 2. The above described conventional system, however, cannot deal with the case where the hosts have different items of mapping information. As a result, when the hosts 1A and 1B share the shared IO device, a limitation occurs that they must have the same mapping information.
Where it is desired that a single host 1 is connected to two or more extended IO apparatuses 2A and 2B, an arrangement can be adopted as shown in FIG. 19 in which the same reference numerals designate the corresponding elements in FIGS. 17 and 18. As seen from the drawing, in order to connect the host 1 to two extended IO apparatuses 2A and 2B, two IO host adaptors 5A and 5B have to be located on the IO bus 3 of the host 1. The maximum number of connections is limited by the number of slots of the IO bus 3 of the host 1. Aside from the above system, such a configuration as a single extended apparatus connected to another extended apparatus through IO port adaptors 7 may be proposed. However, an increase in the number of the extended IO apparatuses leads to an increase in transaction delay, thereby deteriorating the performance of the system.